The present invention relates to a semiconductor device having a packaged structure, and a method of producing the semiconductor device. In particular, the present invention relates to a semiconductor device called a wafer level Chip Size Package (CSP).
Patent Reference has disclosed technology for producing a semiconductor device of this type. FIGS. 4(a) and 4(b) are schematic views showing a post electrode of a conventional semiconductor device, in which FIG. 4(a) is a side view thereof, and FIG. 4(b) is a plan view thereof.
As shown in FIG. 4(a), an organic insulation layer 1 is formed on a passivasion layer of a wafer having an integrated circuit (not shown) formed thereon. A seed layer 2 is formed over a whole surface of the wafer with sputtering, so that plating current flows in a pattern formed with photolithography when a wiring or a post electrode is plated.
A wiring pattern is formed using resist with photolithography, and the wiring pattern is plated using the plating current supplied through the seed layer 2 to form a wiring 3. The wiring 3 is provided for electrically connecting a pad of the integrated circuit and a post electrode 5 (described later). The wiring 3 includes a base portion 4a having an octagon shape at an end portion thereof.
The post electrode 5 having a column shape is formed on the base portion 4a. A post electrode pattern is formed on the base portion 4a using resist with photolithography, and the post electrode pattern is plated using the plating current supplied through the seed layer 2 to form the post electrode 5. The post electrode 5 is provided for electrically connecting a solder terminal or external terminal (not shown) and the wiring 3.
After the post electrode 5 is formed, the resist is removed, and the seed layer 2 exposed between the wiring 3 is etched, thereby electrically isolating the wiring 3.
A sealing resin 6 covers a surface where the wiring 3 and the post electrode 5 are formed. After molding, the sealing resin 6 is ground, so that a top of the post electrode 5 is exposed. The solder terminal (not shown) is formed on the top of the post electrode 5 thus exposed. After the solder terminal is formed, the wafer is ground until a desirable thickness thereof is obtained. Then, the wafer is cut to an individual package with a dicing process, thereby obtaining the semiconductor device.
In the conventional semiconductor device, the base portion 4a of the wiring 3 has a diameter greater than that of the post electrode 5 as shown in FIG. 4(b). A difference between the diameter of the base portion 4a and that of the post electrode 5 depends on an overlapping dimension of photolithography when the post electrode 5 is formed. That is, a size of the base portion 4a is set such that the post electrode 5 is situated on the base portion 4a without shifting out thereof in consideration of production accuracy when the post electrode 5 is formed with photolithography.
Patent Reference: Japanese Patent Publication No. 2000-183090
In the conventional semiconductor device described above, the base portion 4a has the diameter greater than that of the post electrode 5. Accordingly, it is difficult to arrange a large number of wirings between the post electrodes. Further, when the wiring is made smaller to accommodate an increased number of wirings, it is difficult to accurately produce the semiconductor. Further, a configuration surrounding the post electrode becomes more complicated, and a shape varies to larger extent.
Further, when the resist pattern is formed for forming the post electrode, it is necessary to match a mask during photolithography process. Accordingly, it is necessary to provide an area on the wafer for disposing a positioning mark for matching the mask. The positioning mark remains in a final structure of the semiconductor as a defect.
In view of the problems described above, an object of the present invention is to provide a semiconductor device to solve the problems of the conventional semiconductor device.
Further objects and advantages of the invention will be apparent from the following description of the invention.